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fedl7041-05 issue date: dec. 3, 2007 ML7041 audio codec 1/28 general description the ML7041 is a single-channel full duplex codec lsi device which performs mutual transcoding between the analog voice band signals ranging from 300 to 3400 hz and the 64 kbps pcm serial data. provided with such functions as dtmf tone generation, transmit/receive data gain control, side-tone path, and low-dropout regulator, the ML7041 is best suited fo r telephone terminals in digital wireless systems. features ? single 3 v power supply v dd : 2.4 to 3.3 v ? coding format: pcm ? -law/pcm a-law/14-bit linear mode selectable ? pcm interface timing: long frame synchronous timing/short frame synchronous timing selectable ? transmit/receive full-duplex operation ? serial pcm transmission data rate: 64 to 2048 kbps ? low power consumption operating mode: 15 mw typ. (v dd = 3.0 v) power-down mode: 3 ? w typ. (v dd = 3.0 v) ? master clock frequency: 2.048 mhz (compatible with pcm shift clock) ? analog output stage 100 mw (differential type) amplifier output for driving receiver speaker: capable of driving an 8 ? load. 6.6 mw (single type) amplifier output for driving earphones speaker: capable of driving a 32 ?? load. ? built-in two low-dropout regulators (150 ma ? 2) ? built-in four general purpose drivers (150 ma ? 4) ? transmit/receive mute, transmit/r eceive programmable gain control ? built-in side tone path ? built-in dtmf tone generator ? transmit slope filter selectable ? i 2 c bus interface (mcu interface) ? built-in transmit voice signal detector ? package: 48-pin plastic tqfp (tqfp48-p-0707-0.50-k) (ML7041 tb)
fedl7041-05 ML7041 2/28 block diagram a /d slope filter bpf mcu i/f (i 2 c) d/a lpf tone/dtmf gen pcm com-p and pcm expand voice detect 20 k ? 20 k ? 20 k ? ?? 32 ?? sd a scl pd n mc k bclk sync 8 ?? 8 ?? vref sg exto exti spo ? spo+ v dd 20 k ?
fedl7041-05 ML7041 3/28 pin configuration (top view) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ag ear2o ear1o v a1 exto exti v a2 spo? ag2 ag3 spo+ v a3 aggp1 gp1 gp2 gp3 gp4 aggp2 v dd mc k sd a scl pcmin pcmout rg2in rg2o a gr2 rg1in rg1o a gr1 rg2pdn rg1pdn p dn sync bclk dg 48 47 46 45 44 43 42 41 40 39 38 37 sg mic3o mic3? mic3+ mic2o mic2i mic1o mic1i swc swb swa v a 48-pin plastic tqfp
fedl7041-05 ML7041 4/28 pin descriptions pin symbol type description state in power-down mode 1 ag ? analog ground (0 v) ? 2 ear2o o receive side voice amplifier output 2 high impedance 3 ear1o o receive side voice amplifier output 1 high impedance 4 v a1 ? analog power supply 1 (3.0 v) ? 5 exto o receive side voice amplifier output high impedance 6 exti i receive side voice amplifier input ? 7 v a2 ? analog power supply 2 (3.0 v) ? 8 spo? o receive side voice amplifier output? high impedance 9 ag2 ? analog ground 2 (0 v) ? 10 ag3 ? analog ground 3 (0 v) ? 11 spo+ o receive side voice amplifier output+ high impedance 12 v a3 ? analog power supply 3 (3.0 v) ? 13 aggp1 ? general purpose port ground 1 (0 v) ? 14 gp1 o general purpose port 1 out put (open drain) high impedance 15 gp2 o general purpose port 2 out put (open drain) high impedance 16 gp3 o general purpose port 3 out put (open drain) high impedance 17 gp4 o general purpose port 4 out put (open drain) high impedance 18 aggp2 ? general purpose port ground 2 (0 v) ? 19 v dd ? digital power supply (3.0 v) ? 20 mck i master clock input (2.048 mhz) ? 21 sda i/o i 2 c data input/output (pull-up resi ster required) high impedance 22 scl i i 2 c shift clock input ? 23 pcmin i pcm receive signal input ? 24 pcmout o pcm transmit signal output ?h? 25 dg ? digital ground (0 v) ? 26 bclk i pcm data shift clock input ? 27 sync i pcm data shift sync signal input ? 28 pdn i power down control input ?l? 29 rg1pdn i power down input for regulator 1 (3.0 v/0 v) ?l? 30 rg2pdn i power down input for regulator 2 (3.0 v/0 v) ?l? 31 agr1 ? ground for regulator 1 (0 v) ? 32 rg1o o regulator 1 output (3.0 v) ?l? (rg1pdn = ?l?) 33 rg1in i regulator 1 power input (3.6 v) ? 34 agr2 ? ground for regulator 2 (0 v) ? 35 rg2o o regulator 2 power outpu t (3.0 v) ?l? (rg2pdn = ?l?) 36 rg2in i regulator 2 input (3.6 v) ? 37 v a ? analog power supply (3.0 v) ? 38 swa i/o analog switch a ? 39 swb i/o analog switch b ? 40 swc i/o analog switch c ? 41 mic1i i transmit side amplifier 1 inverting input ? 42 mic1o o transmit side amplifier 1 output high impedance 43 mic2i i transmit side amplifier 2 inverting input ? 44 mic2o o transmit side amplifier 2 output high impedance 45 mic3+ i transmit side amplifier 3 non-inverting input ? 46 mic3? i transmit side amplifier 3 inverting input ? 47 mic3o o transmit side amplifier 3 output high impedance 48 sg o analog signal ground (1.4 v) ?l?
fedl7041-05 ML7041 5/28 pin and functional descriptions mic1i, mic1o, mic2i, mic2o, mic3?, mic3+, mic3? transmit analog inputs and outputs for transmit gain adjustment. gains of input levels of the pins can be adjusted using external resisters. mic1i, mic2i, and mic3? are connected to the inverting inputs of the internal transm it amplifiers. mic3+ is connected to the non-inverting inpu t of the internal transmit amplifie r 3. mic1o, mic2o, and mic3o are connected to the internal transmit amplifier outputs. anal og input signals are controlled by the control register (cr1-b7, b6). also, the amplifiers that are not being se lected are deactivated and th eir outputs are put into high impedance state. refer to figure 1 for gain adjustment. ear1o, ear2o, exto, exti, spo?, spo+ receive analog outputs and inputs for receive gain adju stment. ear1o, ear2o, and exto are the receive filter outputs. ear1o and ear2o can directly drive a 32 ? load. spo+ and spo? are differential analog signa l outputs which can directly drive an 8 ? load. the receive side signal outputs can be selected by cr1-b5 and cr1-b4. if the amplifiers connected to ear1o and ear2o are not being selected, the amplifiers are deactivated and their outputs are put into high impedance state. gains of output levels of the pins can be adjusted using the external resistors. the power control is accomplished by cr0-b6. refer to figure 1.
fedl7041-05 ML7041 6/28 figure 1 analog interface a /d 20 k ? ? 20 k ? mic1i mic1o mic2i mic2o mic3? mic3+ mic3o r1 r2 c c c r3 c c c sg vref r4 r5 r6 transmit gain : v mic1o /vi = (r2/r1) : v mic2o /vi = (r4/r3) : v mic3o /vi = (r6/r5) input select :cr1-b7, b6 ?00? -> mic1 :cr1-b7, b6 ?01? -> mic2 :cr1-b7, b6 ?10? -> mic3 :cr1-b7, b6 ?11? -> no-input receive gain :v spo /v exto = (r8/r7) ??? 2 output select :cr1-b5, b4 ?00? -> exto :cr1-b5, b4 ?01? -> ear1o :cr1-b5, b4 ?10? -> ear2o :cr1-b5, b4 ?11? -> no-output vi vi vi ear1o ear2o spo? spo+ exto d/a exti r7 r8 c v exto v spo
fedl7041-05 ML7041 7/28 sg analog signal ground. the output voltage of this pin is approximately 1.4 v. pu t the bypass capacitors 0.1 f ceramic type between this pin and gnd to get the specified noise characteristics. during power-down, this output voltage is 0 v. swa, swb, swc used for an internal analog switch. the pin swb is connected to the pin swa or the pin swc. this is controlled by cr1-b1. rg1pdn, rg1in, rg1o used for regulator 1. the rg1pdn pin is a power down in put. when set to ?l?, the regulator 1 changes to the power down state. since the power down is controlled by a logical or with cr5-b4 of the control register, set cr5-b4 to logic ?0? when using this pin. the rg1in pin is input to the regulator 1. the rg1o pin is output from the regulator 1, whose voltage is 3.0 v. a 1 ? f ceramic type bypass capacitor must be connected between the power input pin and gnd, and a 10 ? f tantalum bypass capacitor must be connected from the output pin to gnd. rg2pdn, rg2in, rg2o used for regulator 2. the rg2pdn pin is a power down in put. when set to ?l?, the regulator 2 changes to the power down state. since the power down is controlled by a logical or with cr5-b5 of the control register, set cr5-b5 to logic ?0? when using this pin. the rg2in pin is the input to the regulator 2. the rg2o pin is the output from the regulator 2, whose voltage is 3.0 v. a 1 ? f ceramic type bypass capa citor must be connected between the power input pin and gnd, and a 10 ? f tantalum bypass capacitor must be connected from the output pin to gnd. note1: the rg1o and rg2o outputs must not be used as the 3 v supply for the ML7041. note2: the rg1in and rg2in should be common near the device and supplied from the same power supply. gp1, gp2, gp3, gp4 general purpose driver output. each pin is controlled by cr5-b1 through cr5-b4. by selecting cr5-b7, the gp1 pin can be controlled by the receive side sign bit. v dd , v a , v a1 , v a2 , v a3 vdd is the digital power supply. va, va1, va2, and va3 are the analog power supply pins. since these pins are separated in the device, connect them as close as possible on the pcb. dg, ag, ag1, ag2, ag3, agr1, agr2, aggp1, aggp2 ground. dg is the digital ground. ag, ag1, ag2, ag3, agr1, agr2, aggp1 and aggp2 are the analog ground. since these pins are separated in the device, connect them as close as possible on the pcb. pdn power down and reset control input. when set to digital ?l?, the device changes to the powe r down state and the control register is reset. since the power down mode is controlled by a logical or with cr0-b5 of the control register, set cr0-b5 to logic ?0? when using this pin. the reset pulse width must be 200 ns or more. be sure to reset the control register after turning on the power. mck master clock input. the frequency must be 2.048 mhz. mck ca n be asynchronous with sync and bclk. if a frequency of bclk is 2.048 mhz, the bclk can be shared with mck. bclk shift clock input for the pcm data. the frequency is set in the range of 64 khz to 2048 khz for a/-law pcm data and set in the range of 128 khz to 2048 khz for linear code selection.
fedl7041-05 ML7041 8/28 sync 8 khz synchronous signal input fo r transmit and receive pcm data. synchronize this signal with bclk signal. this signal is used to indicate the msb of the pcm data stream. pcmout transmit pcm data output. the pcm output signal is output from msb, synchronously with the rising edges of bclk and sync. refer to figure 2. this is a logic output pin so that external pull-up is not required. this pin outputs logic "l" except during effective pcm data bits, and outputs logic "h" during power-down. pcmin receive pcm data input. the pcm input signal is shifted in on the fa lling edge of bclk and is input from msb. refer to figure 2. figure 2 pcm interface basic timing diagram bclk sync msb lsb pcmin or pcmout * 14 bits when linear mode is selected 8 khz (125 s) (b) short frame synchronous interface 8 khz (125 s) bclk sync msb lsb pcmin or pcmout * 14 bits when linear mode is selected (a) long frame synchronous interface
fedl7041-05 ML7041 9/28 sda, scl sda is the serial data input/output pin and scl is the serial clock line input pin. a pull-up register of 1 to 10 k ? is required for the sda pin. the master clock is required when data is written or read. transfer format the control register can be controlled according to the i 2 c bus transfer format. the control register address is 3 bits long and the regi ster data is 8 bits long. the methods of writing and reading of data are shown below. register address 7-bit slave address ?0011010? r/ w ? 0 ? read-back mode bit ?0? sda scl figure 3 i 2 c interface write timing slave address write register addr ess write register data write register add r ess s p a r/ w ?0? read-back mode bit ?0? sda scl figure 4 i 2 c interface read timing: normal mode slave address write register address write register data read slave address r/ w ?1? slave address s r b7 b6 b5 b4 b3 b2 b1 b0 a 2 a 1 a 0 a 2 a 1 a 0 b7 b6 b5 b4 b3 b2 b1 b0 slave address write a a register address s p a r/ w ? 0 ? read-back mode bit ?1? sda scl figure 5 i 2 c interface read timing: read-back mode slave address write register addr ess write register data write slave address b7 b0 a 2 a 1 a 0 a a b6 b1 register data read b7 b0 b6 b1 s a a a p s start condition p stop condition a a cknowledged (ML7041 drive sda to ?0?) s r repeated start condition not acknowledged ML7041 slave address ?0011010? don?t care (?0? or ?1?) a a a register data register data register data register data
fedl7041-05 ML7041 10/28 table 1 shows the register map. table 1 control register map address control and detect data name a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 rw cr0 0 0 0 a/ ? sel spout pon pdn all pdn tx pdn rx slp slp sel lnr r/w cr1 0 0 1 mic sel1 mic sel0 sp sel1 sp sel0 short frame ? sw c/a rx pad r/w cr2 0 1 0 tx on/off tx gain2 tx gain1 tx gain0 rx on/off rx gain2 rx gain1 rx gain0 r/w cr3 0 1 1 side tone gain2 side tone gain1 side tone gain0 tone on/off tone gain3 tone gain2 tone gain1 tone gain0 r/w cr4 1 0 0 dtmf/ others sel tone send ? tone4 tone3 tone2 tone1 tone0 r/w cr5 1 0 1 gp1 sel cr/tone ? rg2pdn rg1pdn gp4c gp3c gp2c gp1c r/w cr6 1 1 0 vox on/off on lvl1 ? ? ? ? ? ? r/w cr7 1 1 1 vox out tx noise1 tx noise0 ? ? ? ? ? r r/w: read/write enable r: read only register
fedl7041-05 ML7041 11/28 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ? ?0.3 to +4.6 v analog input voltage v ain ? ?0.3 to v dd +0.3 v digital input voltage v din ? ?0.3 to v dd +0.3 v storage temperature t stg ? ?55 to +150 ? c operating junction temperature * t jmax ? +150 ? c recommended operating conditions parameter symbol conditio n min. typ. max. unit power supply voltage v dd ? 2.4 ? 3.3 v operating temperature ta ? ?40 +25 +85 ? c operating junction temperature (average) * t jmaxa ? ? ? 105 ? c input high voltage v ih all digital input pins 0.7 ? v dd ? v dd v input low voltage v il all digital input pins 0 ? 0.20 ? v dd v digital input rise time t ir all digital input pins ? ? 50 ns digital input fall time t if all digital input pins ? ? 50 ns digital output load c dl all digital output pins ? ? 100 pf bypass capacitor for sg c sg between sg and ag 0.1 ? ? ? f master clock frequency f mck mck ?0.01% 2.048 +0.01% mhz f bck1 bclk (a/ ? -law) 64 ? 2048 khz bit clock frequency f bck2 bclk (linear) 128 ? 2048 khz synchronous signal frequency f sync sync ? 8.0 ? khz clock duty ratio d clk mck, bclk 40 50 60 % t sb sync ? bclk -100 ? 100 ns sync pulse setting time t bs bclk ? sync 100 ? ? ns synchronous signal width t ws sync 1bclk ? 100 s * the device should be used in such a way that t jmax (average) is less than 105 ? c. t jmax is given by the equation: t jmax = p ?? ? ? ja + ta where p = power dissipation (w) a 48-pin tqfp package is used. ? ? ja = 195 ? c (not mounted on a pcb, in still-air-ambient) ? ? ja = 156 ? c (mounted on a typical pcb, in still-air-ambient) for more details, refer to package information data book.
fedl7041-05 ML7041 12/28 electrical characteristics dc characteristics (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit i dd1 operating mode no signal (v dd = 3.0 v) 0 5.0 11.0 ma i dd2 operating mode no signal (v dd = 3.0 v) spo+, spo? or ear1, 2 is active 0 16.0 32.0 ma power supply current i dd3 power down mode (v dd = 3.0 v, ta = 25 ? c) 0 1.0 10 ? a i ih v i = v dd ? ? 2.0 ? a input leakage current i il v i = 0 v ? ? 1.5 ? a output high voltage v oh i oh = 0.4 ma 0.5 ? v dd ? v dd v output low voltage v ol i ol = ?1.2 ma 0 0.2 0.4 v input capacitance c in ? ? 5 ? pf analog interface characteristics (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit input resistance r inx mic1i, mic2i, mic3?, mic3+ 10 ? ? m ? r lgx1 mic1o, mic2o, mic3o, exto 20 ? ? k ? r lgx2 ear1o, ear2o 32 ? ? ?? output load resistance r lgx3 spo+, spo? differential output 8 ? ? ?? output load capacitance c lgx analog output ? ? 50 pf mic1o, mic2o, mic3o, exto, rl = 20 k ? v o1 ear1o, ear2o, rl = 32 ? ? ? 1.3 v pp v o2 spo+, spo?, (differential output) v dd = 3.0 v, rl = 8 ? ? ? 2.6 v pp output amplitude * v o3 spo? (single output) v dd = 3.0 v, rl = 20 k ???? thd = 1% 2.0 2.6 ? v pp total harmonic distortion thd ear1o, ear2o, spo+, spo? v dd = 3.0 v (at v o1 , v o2 ) ? ? 5.0 % v ofgx1 mic1o, mic2o, mic3o ?40 ? 40 mv offset voltage v ofgx2 ear1o, ear2o, spo+, spo?, exto ?100 ? 100 mv sg output voltage v sg sg ? 1.4 ? v sg output impedance r sg sg ? 40 80 k ? internal switch on impedance r sw all internal analog switches (1.4 v dc bias) ? ? 300 ?? * ?7.7 dbm (600 ? ) = 0 dbm0, +3.17 dbm0 = 1.3 v pp
fedl7041-05 ML7041 13/28 ac characteristics (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) condition parameter symbol frequency (hz) level (dbm0) others min. typ. max. unit l oss t1 0 to 60 25 ? ? db l oss t2 300 to 3000 ?0.15 ? 0.20 db l oss t3 1020 reference db l oss t4 3300 ?0.15 ? 0.80 db l oss t5 3400 0 ? 0.80 db transmit frequency response l oss r6 3968.75 0 ? 13 ? ? db l oss r1 0 to 3000 ?0.15 ? 0.20 db l oss r2 1020 reference db l oss r3 3300 ?0.15 ? 0.80 db l oss r4 3400 0 ? 0.80 db receive frequency response *2 l oss r5 3968.75 0 ? 13 ? ? db sd t1 3 35 ? ? db sd t2 0 35 ? ? db sd t3 ?30 35 ? ? db sd t4 ?40 28 ? ? db transmit signal to distortion ratio sd t5 1020 ?45 *1 23 ? ? db sd r1 3 35 ? ? db sd r2 0 35 ? ? db sd r3 ?30 35 ? ? db sd r4 ?40 28 ? ? db receive signal to distortion ratio *2 sd r5 1020 ?45 *1 23 ? ? db gt t1 3 ?0.5 ? 0.5 db gt t2 ?10 reference db gt t3 ?40 ?0.5 ? 0.5 db gt t4 ?50 ?1.0 ? 1.0 db transmit gain tracking gt t5 1020 ?55 ? ?1.2 ? 1.2 db gt r1 3 ?0.5 ? 0.5 db gt r2 ?10 reference db gt r3 ?40 ?0.5 ? 0.5 db gt r4 ?50 ?1.0 ? 1.0 db receive gain tracking *2 gt r5 1020 ?55 ? ?1.2 ? 1.2 db *1 use the p-message weighted filter. *2 exto output
fedl7041-05 ML7041 14/28 ac characteristics (continued) (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) condition parameter symbol frequency (hz) level (dbm0) others min. typ. max. unit n idlt ? mic1i, mic2i, mic3 ? = sg *1 ? ? ?68 dbmop idle channel noise n idlr ? ? *1,*2,*4 ? ? ?72 a vt mic1o, mic2o, mic3o 0.285 0.320 *3 0.359 vrms absolute signal amplitude a vr 1020 0 exto 0.285 0.320 *3 0.359 vrms p srrt 30 ? ? db power supply noise rejection ratio p srrr noise frequency: 0 to 50 khz noise level: 50 mvpp ? 30 ? ? db t sdx 0 ? 200 ns t xd1 0 ? 200 ns t xd2 0 ? 200 ns digital input/output timing pcm interface t xd3 ? 1 lsttl + 100 pf see figure 6 0 ? 200 ns pcmin setup time t ds 100 ? ? ns pcmin hold time t dh ? ? see figure 6 100 ? ? ns f scl 0 ? 100 khz t buf 4.7 ? ? ? s t hd:sta 4.0 ? ? ? s t low 4.7 ? ? ? s t high 4.0 ? ? ? s t su:sta 4.7 ? ? ? s t hd:dat 0 ? ? ? s t su:dat 250 ? ? ns i 2 c interface timing t su:sto ? cl = 50 pf see figure 7 4.0 ? ? ? s *1 use the p-message weighted filter. *2 pcmin input code ?11010101? (a-law) ?11111111? ( ? -law) *3 0.320 vrms = 0 dbm0 = ?7.7 dbm *4 exto output
fedl7041-05 ML7041 15/28 ac characteristics (dtmf and other tones) (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit frequency difference d ft dtmf tones, other tones ?1.5 ? +1.5 % v tl dtmf (low) and other tones ?18 ?16 ?14 dbm0 v th transmit tones (gain setting of 0 db) dtmf (high) ?16 ?14 ?12 dbm0 v rl dtmf (low) ?4 ?2 0 dbm0 original (reference) tones signal level *5 v rh receive tones (gain setting of ?6 db) dtmf (high) and other tones ?2 0 +2 dbm0 relative level of dtmf tones r dtmf v th /v tl , v rh /v rl +1 +2 +3 db *5 not including programmable gain set values ac characteristics (programmable gain stages) (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit gain accuracy d g all gain stages, to programmed value ?1 0 +1 db ac characteristics (voice detect function) (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit t von ? 5 ? ms voice detection time t vof silence ? voice (voice/silence differential: 10 db) 140 160 180 ms voice detection accuracy d vx for detection level set values by cr6-b6 ?2.5 0 2.5 db
fedl7041-05 ML7041 16/28 ac characteristics (general purpose drivers) (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit output voltage v o ? ? 0.7 v output load resistance r o i out = 150 ma, gp1 - gp4 20 ? ? ?? ac characteristics (regulator 1 and 2) (v dd = 2.4 to 3.3 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit v i1 i out = 50 ma 3.3 3.6 4.1 v input voltage v i2 i out = 150 ma 3.5 3.6 4.1 v output voltage v o rgin = 3.6 v, i out = 0 ma, ta = 25 ? c 2.93 3.00 3.07 v load current i o 3.5 v < rgin < 4.1 v ? ? 150 ma dropout voltage v drop i out = 150 ma , rgin = 3.6 v ? ? 200 mv output voltage line regulation dv o /dv i i out = 50 ma 3.3 v < rgin < 4.1 v, ta = 25 ? c ? 0.1 1.25 %/v standby current i stanby rg1pdn = 0, rg2pdn = 0 0.1 10 a
fedl7041-05 ML7041 17/28 timing diagram transmit side pcm timing (normal synchronous interface) transmit side pcm timing (short frame synchronous interface) receive side pcm timing (nor mal synchronous interface) receive side pcm timing (short frame synchronous interface) figure 6 pcm interface timing msb lsb 0 t ws t sb t dh bclk sync pcmin 1 2 3 4 5 6 7 8 9 1 0 msb lsb t xd3 0 t ws t xd1 t xd2 bclk sync pcmout 1 2 3 4 5 6 7 8 9 1 0 t sb t bs msb lsb t xd3 0 t sdx t ws t sb t xd1 t xd2 bclk sync pcmout 1 2 3 4 5 6 7 8 9 1 0 when t sb >= 0, the delay of the msb is defined as t xd1 . when t sb < 0, the delay of t he msb is defined as t sdx . msb lsb 0 t ws t dh bclk sync pcmin 1 2 3 4 5 6 7 8 9 10 t sb t bs t ds t ds
fedl7041-05 ML7041 18/28 i 2 c interface figure 7 i 2 c interface timing sda scl p t buf s t hd:sta t low t hd:dat t high t su:dat sr t su:sta t hd:sta p t su:sto f scl
fedl7041-05 ML7041 19/28 functional description control registers cr0 (basic operating mode 1) note: the initial value means a value set when the device is reset by the pdn pin. b7 b6 b5 b4 b3 b2 b1 b0 cr0 a/ ? sel spout pon pdn all pdn tx pdn rx slp slp sel lnr initial value 0 0 0 0 0 0 0 0 b7 ....... pcm interface companding law select 0: ? -law 1: a-law b6 ....... power-on control for output amplifies (spo+, spo ? ) 0: power down 1: power on b5 ....... power down (entire circuitry) 0: power on 1: power down ored with the inverted pdn signal. when using this data, set pdn to ?l?. the control registers are not reset by this signal. b4 ....... power down (transmit only) 0: power on 1: power down b3 ....... power down (receive only) 0: power on 1: power down b2 ....... slope filter enable 0: slope f ilter disable 1: slope filter enable b1 ....... slope filter frequency response se lect 0: case1 1: case2 either case1 or case2 can be selected in figure 8. b0 ....... pcm interface linear code select 0: pcm companding law selected by cr0-b7 1: 14-bit linear code (2?s complement) figure 8 slope filter frequency characteristics ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 0 500 1000 1500 2000 2500 3000 3500 4000 gain [db] frequency [hz] case1 case2
fedl7041-05 ML7041 20/28 cr1 (basic operating mode 2) b7 b6 b5 b4 b3 b2 b1 b0 cr1 mic sel1 mic sel0 sp sel1 sp sel0 short frame ? sw c/a rx pad initial value 0 0 0 0 0 0 0 0 b7, b6?.. selection of an input amplifier to encoder (b7, b6) = (0, 0): mic1 = (0, 1): mic2 = (1, 0): mic3 = (1, 1): no input amplifiers which are not selected are powere d down and their outputs go in the high impedance state. b5, b4?.. selection of an output amplifier (b5, b4) = (0, 0): exto = (0, 1): ear1o = (1, 0): ear2o = (1, 1): no output amplifiers which are not selected are powere d down and their outputs go in the high impedance state. b3 ??. short frame synchronous interface select 0: long frame synchronous interface, 1: short frame synchronous interface b2 ??. not used. when writing data, write ?0?. b1 ??. analog switch control 0: the swb pi n is internally connected to the swa pin. 1: the swb pin is internally connected to the swc pin. the unconnected pins go in a high impedance state. b0 ??. receive side pad 0: no pad 1: a pad of 12 db loss is inserted in the receive side voice path.
fedl7041-05 ML7041 21/28 cr2 (pcm codec operating mode setting and transmit/receive gain adjustment) b7 b6 b5 b4 b3 b2 b1 b0 cr2 tx on/off tx gain2 tx gain1 tx gain0 rx on/off rx gain2 rx gain1 rx gain0 initial value 0 0 1 1 0 0 1 1 b7.................. transmit side pcm signal on/off 0: on 1: off b6, b5, b4 ..... transmit side signal gain adjustment (refer to table 2) b3.................. receive side pcm signal on/off 0: on 1: off b2, b1, b0 ..... receive side signal gain adjustment (refer to table 2) table 2 transmit/receive gain settings b6 b5 b4 transmit gain b2 b1 b0 receive gain 0 0 0 ?6 db 0 0 0 ?12 db 0 0 1 ? 4 d b 0 0 1 ? 9 d b 0 1 0 ? 2 d b 0 1 0 ? 6 d b 0 1 1 0 d b 0 1 1 ? 3 d b 1 0 0 + 2 d b 1 0 0 0 d b 1 0 1 + 4 d b 1 0 1 + 3 d b 1 1 0 + 6 d b 1 1 0 + 6 d b 1 1 1 + 8 d b 1 1 1 + 9 d b the above gain settings table shows the transmit/recei ve voice signal gain settings and the transmit side gain settings for dtmf tones and other tones. the dt mf and other tone transmit signals are enabled by cr4-b6, and the gain setting is referenced to the levels shown below. dtmf tones (low group): .............................. ? 16 dbm0 dtmf tones (high group) and other tones:... ? 14 dbm0 for example, if the transmit gain set value is set to +8 db (b6, b5, b4) = (1,1,1), then the following tones are output at the pcmout pin. dtmf tones (low group): .............................. ? 8 dbm0 dtmf tones (high group) and other tones:... ? 6 dbm0 gains of the side tone (path to receive side from tr ansmit side) and the receive side tone can be set by register cr3.
fedl7041-05 ML7041 22/28 cr3 (side tone and other tone generator gain setting) b7 b6 b5 b4 b3 b2 b1 b0 cr3 side tone gain2 side tone gain1 side tone gain0 tone on/off tone gain3 tone gain2 tone gain1 tone gain0 initial value 0 0 0 0 0 0 0 0 b7, b6, b5 ..........side tone path gain setting (refer to table 3) b4 .......................tone generato r on/off 0: off 1: on b3, b2, b1, b0 ....tone generator gain adjustment for receive side (refer to table 4) table 3 side tone gain settings b7 b6 b5 side tone path gain 0 0 0 off 0 0 1 ?15 db 0 1 0 ?13 db 0 1 1 ?11 db 1 0 0 ?9 db 1 0 1 ?7 db 1 1 0 ?5 db 1 1 1 ?3 db table 4 receive side tone generator gain settings b3 b2 b1 b0 tone generator gain b3 b2 b1 b0 tone generator gain 0 0 0 0 off 1 0 0 0 ?20 db 0 0 0 1 ?34 db 1 0 0 1 ?18 db 0 0 1 0 ?32 db 1 0 1 0 ?16 db 0 0 1 1 ?30 db 1 0 1 1 ?14 db 0 1 0 0 ?28 db 1 1 0 0 ?12 db 0 1 0 1 ?26 db 1 1 0 1 ?10 db 0 1 1 0 ?24 db 1 1 1 0 ?8 db 0 1 1 1 ?22 db 1 1 1 1 ?6 db the receive side tone generator gain settings shown in table 4 are referenced to the following levels as a reference. dtmf tones (low group): .............................. +4 dbm0 dtmf tones (high group) and others tones: . +6 dbm0 for example, if the tone generator gain set value is se t to ?6 db (b3, b2, b1, b0) = (1, 1, 1, 1), then tones at the following levels are output at exto. dtmf tone (low group): ................................ ?2 dbm0 dtmf tone (high group) a nd other tones:..... 0 dbm0
fedl7041-05 ML7041 23/28 cr4 (tone generator operating mode and frequency select) b7 b6 b5 b4 b3 b2 b1 b0 cr4 dtmf/ others sel tone send ? tone4 tone3 tone2 tone1 tone0 initial value 0 0 0 0 0 0 0 0 b7 ............................dtmf or other tones select 0: others 1: dtmf b6 ............................tone transmit enable (transmit side) 0: voice signal transmit 1: tone transmit b5 ............................not used. when writ ing data, write ?0?. b4, b3, b2, b1, b0 ..tone frequency setti ng (refer to tables 5-1 and 5-2) (a) b7 = 1 (dtmf tone) table 5-1 tone generator frequency settings b4 b3 b2 b1 b0 frequency b4 b3 b2 b1 b0 frequency * 0 0 0 0 697 hz + 1209 hz * 1 0 0 0 852 hz + 1209 hz * 0 0 0 1 697 hz + 1336 hz * 1 0 0 1 852 hz + 1336 hz * 0 0 1 0 697 hz + 1477 hz * 1 0 1 0 852 hz + 1477 hz * 0 0 1 1 697 hz + 1633 hz * 1 0 1 1 852 hz + 1633 hz * 0 1 0 0 770 hz + 1209 hz * 1 0 0 0 941 hz + 1209 hz * 0 1 0 1 770 hz + 1336 hz * 1 1 0 1 941 hz + 1336 hz * 0 1 1 0 770 hz + 1477 hz * 1 1 1 0 941 hz + 1477 hz * 0 1 1 1 770 hz + 1633 hz * 1 1 1 1 941 hz + 1633 hz *undefined (b) b7 = 0 (other tones) table 5-2 tone generator frequency settings b4 b3 b2 b1 b0 frequency b4 b3 b2 b1 b0 frequency 0 0 0 0 0 2730 hz/2500 hz 8 hz wamb. 1 0 0 0 0 1200 hz 0 0 0 0 1 2000 hz/2667 hz 8 hz wamb. 1 0 0 0 1 1300 hz 0 0 0 1 0 1000 hz/1333 hz 8 hz wamb. 10010 0 0 0 1 1 ? 1 0 0 1 1 1477 hz 0 0 1 0 0 ? 1 0 1 0 0 1633 hz 0 0 1 0 1 ? 1 0 1 0 1 2000 hz 0 0 1 1 0 ? 1 0 1 1 0 2100 hz 0 0 1 1 1 ? 1 0 1 1 1 0 1 0 0 0 ? 1 1 0 0 0 2400 hz 0 1 0 0 1 400 hz 1 1 0 0 1 0 1 0 1 0 440 hz 1 1 0 1 0 2500 hz 0 1 0 1 1 480 hz 1 1 0 1 1 0 1 1 0 0 ? 1 1 1 0 0 0 1 1 0 1 667 hz 1 1 1 0 1 2700 hz 0 1 1 1 0 800 hz 1 1 1 1 0 0 1 1 1 1 1000 hz 1 1 1 1 1 3000 hz
fedl7041-05 ML7041 24/28 cr5 (regulator control, general purpose driver control) b7 b6 b5 b4 b3 b2 b1 b0 cr5 gp1 sel cr/tone ? rg2pdn rg1pdn gp4c gp3c gp2c gp1c initial value 0 0 0 0 0 0 0 0 b7 .......................selection of how to control general purpose driver 1. 0: control register cr5-b0 1: gp1 is controlled by a sign bit of the receiver. b6 .......................not used b5 .......................power down cont rol for regulator 2 0: power down 1: power on when using this data, set the rg2pdn pin at a ?l? level. b4 .......................power down cont rol for regulator 1 0: power down 1: power on when using this data, set the rg1pdn pin at a ?l? level. b3, b2, b1, b0 ....general purpose driver control 0: off (high impedance) 1: on (?l? output) cr6 (vox function control) b7 b6 b5 b4 b3 b2 b1 b0 cr6 vox on/off on lvl1 ?? ?? ?? ?? ?? ?? initial value 0 0 * 0 0 0 0 0 b7 .................................voice/silence detect function on / off 0: off 1: on if b7 is set to a logic ?1?, b3 should be set to a logic ?1?. b6 .................................voice detector level setting 0: ?26 dbm0 1: ?38 dbm0 b5 .................................reserved bit. when writing data, write ?0?. b4, b3, b2, b1, b0 .......not used. when writing data, write ?0?. cr7 (detect register, read only) b7 b6 b5 b4 b3 b2 b1 b0 cr7 vox out tx noise level1 tx noise level0 ?? ?? ?? ?? ?? initial value 0 0 0 * * * * * *used for testing the device and undefined b7 .............................. transmit side voice/silence detecti on 0: silence 1: voice detect b6, b5........................ transmit side silenc e detect level (indicator) (0,0): below ?50 dbm0 (0,1): ?40 to ?50 dbm0 (1,0): ?30 to ?40 dbm0 (1,1): above ?30 dbm0 note: these outputs are enabled only when the vox (cr6-b7) = ?1?. b4, b3, b2, b1, b0 .... not used
fedl7041-05 ML7041 25/28 application circuit a/d slope filter bpf mcu i/f (i 2 c) d/a lpf tone/dtmf gen pcm com- pand pcm expand voice detect 20 k ? ? ? ?? 32 ?? sda scl p dn mck bclk sync other ic other ic buzzer lcd key pad vibrator mic gnd v dd r r c c r c speaker r earphone out in speaker phone 8 ?? 8 ? ? r vref sg exto exti spo? spo+ hands free kit r c c r c c=0.1 ? f sg v dd (3.0 v) 10 ? ? ? ?
fedl7041-05 ML7041 26/28 package dimensions tqfp48-p-0707-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 0.13 typ. 5 rev. no./last revised 4/oct. 28, 1996 notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package co de and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl7041-05 ML7041 27/28 revision history page document no. date previous edition current edition description fedl7041-01 nov. 2000 D D 1 st edition fedl7041-02 jun. 16, 2004 8 8 more cl arification of pc mout output state 11 11 addition of t sb fedl7041-03 nov. 2, 2005 17 17 addition of t sb addition of description about t xd1 and t sdx fedl7041-04 mar. 2, 2006 24 24 addi tion of description about cr6-b3 14 14 addition of t ds, t dh 17 17 corrected figure 6 pcm interface timing receive side pcm timin g fedl7041-05 dec. 3, 2007 23 23 addition of ? D ? to blanks in table 5-2 tone generato r
fedl7041-05 ML7041 28/28 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the inform ation specified in this document. however, should you incur any damage arising from any inaccu racy or misprint of such informa tion, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever fo r any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhan ce the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis se miconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical inst rument, transportation equipm ent, aerospace machinery, nuclear-reactor controller, fuel-cont roller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products fo r the above special purposes. if a product is intended to be used for any such special purpose, please cont act a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

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